1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device including transistors that have different sizes, and to a method of manufacturing the semiconductor device.
2. Description of the Related Art
Nowadays, electronics, e.g., equipment such as a personal computer, is being developed to perform a greater number of functions, to occupy less space and to operate at higher speeds. Semiconductor memory devices are used to store information in such electronics. Thus, semiconductor memory devices are being required to operate at higher speeds and to possess greater storage capacities. Accordingly, semiconductor memory devices along with their methods of manufacture are being developed with an aim towards improving the degrees of integration, reliability, response times, etc. of the devices.
One basic unit of a semiconductor memory device is a metal-oxide-semiconductor field-effect transistor (MOSFET). A MOSFET typically operates at a high speed under a relatively low voltage. Therefore, MOSFETs are being constantly refined so that they can become more highly integrated.
Highly integrated transistors are provided in what is referred to as a cell region of a semiconductor memory device. Transistors may also be provided in a core/peripheral region of a semiconductor memory device where circuits for driving the transistors in the cell region (hereinafter “cell transistors”) are formed. The widths of the gates and the spacing between the gates of these core/peripheral transistors are greater than those of the cell transistors. Thus, source/drain regions in a semiconductor substrate at both sides of a gate electrode of a cell transistor tend to be very narrow.
The narrower the source/drain regions are, the smaller is the area (hereinafter “contact area”) at which electrical contact can be established with a source/drain region. Thus, narrow source/drain regions are prone to contact failures. Furthermore, the contact resistance is high when the contact area is small. Consequently, transistors having small contact areas may also have poor operating characteristics.
To provide a sufficiently large contact area, spacers on sidewalls of the gate structure are conventionally made as thin as possible. However, when the spacers are too thin, impurities in the source/drain regions may diffuse into the semiconductor substrate under the gate structures. This reduces the channel length of the transistor. When the channel length is too short, the discharge in the drain region may be greater than the discharge by the gate structure. This undesired effect, in which the transistor does not perform a switching function, is referred to as a short channel effect.